Current Imaging using Magnetic Field Sensors

As process technologies of integrated circuits become more complex and the industry moves toward advanced packaging like flip-chip and stacked die, present tools and techniques are having increasing difficulty in meeting failure analysis needs [1]. With gate sizes approaching 65 nm, “killer defects” may only be a few nanometers in size. In some cases, the defects are nonvisible, i.e. there is no particle that can be imaged by optical microscope or SEM. The increasing number of transistors on a die is also requiring more levels of metal interconnect, which can limit thermal and optical techniques. The more complex devices today have 6 levels of metal, but many companies see 10 to 12 levels in the near future. Further complicating die level analysis are the trends in packaging technology. Flip-chip packaging requires that nondestructive measurements be made through the silicon substrate, and stacked die packaging can require that data is taken through multiple die and packaging materials. The package substrates for these new integrated circuits are also becoming more complex with finer line dimensions approaching 10 μm and many layers of metallization often with several ground and power planes that complicate nondestructive analysis. To meet the needs of failure analysis for some present and most future applications, techniques are needed that are not obstructed by these complications. To some extent this can be accomplished in electrical test through scan architectures once adopted. However, diagnosis of defects using such methods is limited to one logical node or wire, which can often be greater than 200 μm in length and traverse many levels. Further, such diagnostic methods are often non-existent for high current failures and faults in analog devices.